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This is a hybrid role with four days per week at Cisco’s Yerevan office.Meet the TeamThe Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. We design the networking hardware for Enterprises and Service Providers of various sizes, the Public Sector, and Non-Profit Organizations across the world. Cisco Silicon One (#CiscoSiliconOne) is the only unifying silicon architecture in the market that enables customers to deploy the best-of-breed silicon from Top of Rack (TOR) switches all the way through web scale data centers and across service provider, enterprise networks, and data centers with a fully unified routing and switching portfolio. Come join us and take part in shaping Cisco's ground-breaking solutions by designing, developing and testing some of the most complex ASICs being developed in the industry.Your ImpactYou will be a key member of the Silicon One development organization, collaborating closely with Front-end RTL and backend physical design teams to gain a deep understanding of chip architecture. Your primary focus will be to drive high-quality Design for Test (DFT) verification, ensuring robust and reliable silicon solutions that meet Cisco’s standards for performance and innovation.



This cross-functional teamwork is essential to delivering advanced networking silicon aligned with Cisco Silicon One’s scalable and adaptable architecture.Taking part in all aspects of digital design, from micro-architecture to RTL design and qualification.Sub-system/SoC integration and verification.Review/enhancement of RTL codes.Improve flows and methodologies to streamline IP/SoC development and integration.Work closely with the verification team for complex debugs to resolve verification failures.Close interaction with physical design team to reach better physical design QoR.Minimum Qualifications5+ years of industry experience in ASIC digital design.Proficient in Verilog/System Verilog coding.Experience with front-end tools (Verilog simulators, linting, CDC checkers, synthesis, formal verification).Experience with industry standard interface protocols such as AMBA(AXI, APB, AHB), JTAG etc, memories.Ability to write scripts using Python, Tcl, Make.Good communications skills, self-motivated and well-organized.Preferred QualificationsFamiliarity with power optimization techniques, power intent (UPF), power estimation.Familiarity with DFT/MBIST is a plus#J-18808-Ljbffr

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📌 Senior Rtl Design Engineer (Capitan)
🏢 Cisco Systems
📍 Capitan