This is a hybrid role with four days per week at Cisco’s Yerevan office.
Meet the Team
Our team is at the forefront of innovation, specializing in memory layout implementation for the Cisco Silicon One platform that powers the world’s most advanced switches and routers. We are a dynamic, international team dedicated to pushing the boundaries of high-performance networking technology. We offer a unique environment where technical excellence meets real-world impact. We value transparency, clear communication, and a collaborative spirit that bridges geographical divides to deliver ground breaking silicon solutions.
Your Impact
Drive the physical design strategy for high-performance memory and SRAM blocks, ensuring alignment with aggressive power, performance, and area targets. Architect complex layout solutions while providing technical leadership to elevate the team’s collective proficiency. Execute critical post-layout validation cycles to guarantee silicon-level reliability and seamless integration across multi-module subsystems.
Lead efforts to enhance layout automation frameworks to reduce design iteration time and increase total velocity. Achieve operational excellence by delivering high-integrity, scalable silicon components that define the next generation of Cisco networking hardware.
Minimum Qualifications
- Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
- 10+ years of total professional experience in physical design or layout with 3+ years of hands-on experience specifically in SRAM layout implementation.
- Expert-level proficiency working with industry-standard EDA tools such as Cadence or Synopsys.
- In-depth experience with advanced node technologies such as TSMC 22nm, 12nm, 7nm, 5nm, or 2nm.
Preferred Qualifications
- Proven ability to mentor and guide cross-functional teams through complex project lifecycles.
- Advanced analytical problem-solving skills, specifically in resolving EM/IR closure bot