Cisco Systems, Inc. in Yerevan invites a senior ASIC design engineer to lead RTL-to-GDSII physical implementation and signoff.
You will collaborate with Front-End teams to translate architecture into optimal physical design, perform synthesis, floorplanning, placement, Clock Tree Synthesis, and routing while optimizing power, performance, and area. Join a integral team delivering silicon excellence for the AI era.
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📌 Senior ASIC Physical Design Engineer - RTL to GDSII (Villavicencio)
🏢 Cisco Systems
📍 Villavicencio
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